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Hardware Engineer

Median Package
Xilinx

$145k

Total / Year

$125k

Base

$13k

Stock

$7k

Bonus

Xilinx

San Jose, CA

E5

Level

5

Yrs At Comp.

5

Yrs Exp.

Latest Salary Submissions
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Company
Location | Date
Level Name
Tag
Years of Experience
Years at Company / Years of Experience
Total Compensation
Base | Stock | Bonus
Xilinx

San Jose, CA | 8/8/21

E8

Validation

3 / 15
$271,000

180k | 72k | 19k

Xilinx

Hsin-chu, TP, Taiwan | 8/6/21

E6

FPGA Design

0 / 8
$90,000

72k | 18k | 0k

Xilinx

San Jose, CA | 7/27/21

E5

SoC Design

5 / 5
$175,000

125k | 35k | 15k

Xilinx

San Jose, CA | 7/18/21

E7

Embedded Systems

2 / 8
$200,000

157k | 25k | 18k

Xilinx

San Jose, CA | 7/10/21

E8

FPGA Design

8 / 8
$310,000

185k | 95k | 30k

Xilinx

Hyderabad, TS, India | 6/30/21

E7

Verification

10 / 15
$81,000

52k | 22k | 7k

Xilinx

Hyderabad, TS, India | 6/22/21

E9

FPGA Design

13 / 20
$134,000

101k | 19k | 13k

Xilinx

Hyderabad, TS, India | 6/5/21

E6

SoC Design

8 / 8
$54,000

38k | 12k | 4k

Xilinx

San Jose, CA | 5/27/21

E5

ASIC Design

3 / 14
$220,000

160k | 40k | 20k

Xilinx

San Jose, CA | 5/23/21

E7

Analog

2 / 8
$207,000

159k | 40k | 8k

Showing 1 to 10 of 22 rows rows per page
Vesting Schedule

25%

25%

25%

25%

YR 1

YR 2

YR 3

YR 4

Stock Type

RSU

At Xilinx, RSUs are subject to a 4-year vesting schedule: 25% vests at the end of each year (cliff).

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